The present invention relates to a logic circuit arrangement which comprises signal input means and signal output means and flux quanta circuits comprising Josephson junctions. The flux quanta are used for carrying digital information.
The invention also relates to an arrangement for processing digital information comprising a number of logic elements, for example one or more of any combination of AND elements, OR elements and NOT elements each of which comprises input and output means and wherein single flux quanta are used as carriers of digital information.
Still further the invention relates to a method for stabilizing a logic circuit arrangement comprising a number of logic elements using flux quanta as information carriers.
Most common today are semiconductor-transistor-based integrated circuits. In semi-conductor logic, digital information is represented as voltage levels wherein the voltage level differences are determined by the electronic band gap. However, circuits based on semiconductor logic have a limited frequency of operation, i.e. it is not as high as could be desired for a number of applications and moreover the power dissipation is not as low as sometimes wanted or needed. This means that for a number of applications these values are not satisfactory.
Therefore a considerable amount of research within superconducting electronics has been done and among others a Rapid Single Flux Quantum (RSFQ) circuit family has been developed. This is based on superconductor integrated circuits and use Josephson junctions. Josephson junction technologies as such have been found advantageous for digital applications among others since the intrinsic switching speed of Josephson junctions is very high, such as around a few picoseconds. Moreover the power dissipation is low and the fabrication technologies are simple as compared to semiconductor transistors for corresponding devices.
In "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Teraherz-Clock-Frequency Digital Systems" by K. K. Likharev and V. K. Semenov in IEEE Transactions on Applied Superconductivity, Vol 1, No 1, March 1991 a rapid single flux quantum (RSFQ) circuit family is presented where the logic is based on processing of single flux quanta wherein each digital information bit is represented by a single flux quantum or a fluxon. Therefore it is, particularly at higher frequencies, easily subjected to bit errors and SFQ-to-DC converters are required as input/output interfaces of an RSFQ chip. These converters serve the purpose of converting digital voltage levels to SFQ pulses and vice versa. The circuit is fully superconducting and the RSFQ logic requires a better magnetic field shielding the larger the circuit is in order to provide shielding from external magnetic fields.
In "SAIL High Temperature Superconductor Digital LOGIC: Improvements and Analyses" by S. M. Schwarzbek et al in IEEE Transactions on Applied Superconductivity, Vol. 3 No 1, March 1993, another SQUID based scheme, a so called Series Array Interferometer Logic, (SAIL) is provided. This logic has similarities with CMOS but it suffers from not being fast enough to compete with the fastest (at room temperature) semiconductor logic circuits.
Moreover flux flow transistor based logic (SFFT) is attractive in so far as it is dual to Field Effect Transistor (FET) logic, but it is inherently slow compared with the RSFQ logic and moreover the power dissipation is several orders of magnitude higher.
Moreover single flux quanta (SFQ) based circuits are known wherein the SFQs are used as digital carriers. However, then resistors are used for the interconnection of active elements. The circuit parameters of these devices have very small margins.
The above mentioned RSFQ logic, although being comparatively fast and having a comparatively low power dissipation, still leaves a lot to desire among others as far as speed and power dissipation is concerned. Moreover, elements based on this logic require additional equipment in order to interface with for example semiconductor circuits since digital voltage levels have to be converted to SFQ pulses and vice versa.